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Coloriage pat patrouille IP Listing

2270 IP Cores (2001 - 2040)

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32G PHY in GF (12nm, N7)

The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY ...

2001
32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)

The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is ...

2002
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, ...

2003
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, ...

2004
PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture

The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specifications, and can be configured by the user to ...

2005
PCIe 6.0 PHY for TSMC N6

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip ...

2006
112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient ...

2007
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N7, N5A, N3A)

Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial ...

2008
LPDDR4 multiPHY V2 in UMC (28nm)

The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring ...

2009
MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A

Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial ...

2010
PCIe 6.0 PHY IP for TSMC N3E

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip ...

2011
HBM3 PHY IP on TSMC N5

The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications ...

2012
PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique ...

2013
PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)

The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Express 7.0 specification, and can be configured by the user to ...

2014
集中式实时处理器IP核

我们根据项目的要求为我们的加密解决方案提供了许多配置。与竞争对手的设计相比，CRP1在整个测试过程中使用的逻辑单元减少了25%，同时保持了相同的性能水平。此外，当应用速度优化...

2015
24-bit Cap-less ADC PLL-less 2 channels

The sADC-H1-LR.02 is a mixed (analog and digital) Virtual Component containing 2 mono ADCs, and additional functions offering an ideal mixed-signal front-end for low-power and high-quality audio ...

2016
AVC/H.264 Video Encoder with Compressed Frame Store

The H264-E-CFS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an energy-efficient hardware architecture that ...

2017
MIPI I3C Basic Target

The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C-BasicSM specification. ...

2018
MIPI I3C Basic Secondary Controller

The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C BasicSM specification. As a secondary controller, ...

2019
GDDR7 PHY & Controller

Innosilicon GDDR7 PHY is fully compliant to the JEDEC GDDR7 standard, supporting up to 32Gbps for PAM3 GDDR7. In pam3 mode, the byte consists of ten DQ and one DQE signals, the GDDR7 also supports ...

2020
MCR DDR5 PHY

The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM devices. It is optimized for low power ...

2021
LPDDR4x Secondary/Slave (memory side!) PHY

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP provides the unique opportunity to transmit ...

2022
LPDDR5 Secondary/Slave (memory side!) PHY

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP provides the unique opportunity to transmit ...

2023
LPDDR5X Secondary/Slave (memory side!) PHY

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP provides the unique opportunity to transmit ...

2024
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs

iNoCulator is a cloud-active EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to measure throughput and latency, power requirements ...

2025
Ethernet TSN Switch IP Core - Efficient and Massively Customizable

Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide an optimized custom IP core within days ...

2026
Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable

Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide an optimized custom IP core within days ...

2027
Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable

Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide an optimized custom IP core within days ...

2028
HSSTP PHY TX 5nm (1.5 Gbps, 3 Gbps, and 6 Gbps)

The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes features like RO PLL, automatic resistor calibration, ...

2029
I2C Controller

I2C Dual mode IP ( master and slave mode) with APB interface to support the standard I2C Bus Protocol and APB5 Interface on the Application side. It is an Inter Integration Circuit IP that ...

2030
DisplayPort 1.4 IP-core

Introducing our DisplayPort 1.4 IP-core – the perfect solution for your DisplayPort needs! This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX). ...

2031
ISP, Image Signal Processing, Real-time Pixel Processor for Automotive

Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed for high-performance imaging applications. ...

2032
HDMI 20 TX/RX PHY

The HDMI Rx PHY is the physical layer of an HDMI receiver. The HDMI Rx PHY implements the analog front-end (AFE) of an HDMI receiver, the sampling and deserialization of the three data streams, ...

2033
Neoverse Compute Subsystems V3 (CSS V3)

The High-Performance Arm V3 Platform Performance-Optimized and Validated by Arm Arm Neoverse CSS V3 is the fastest path to building high-performance, TCO-optimized cloud CPUs or custom AI ...

2034
Neoverse Compute Subsystems N3 (CSS N3)

The Performance-per-Watt Leading Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets Highly configurable to target 5G, DPU, and enterprise networking markets, Arm Neoverse ...

2035
Neoverse Compute Subsystems N2 (CSS N2)

Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem Arm Neoverse CSS N2 is the first generation of Neoverse CSS ...

2036
Ultra-small footprint, static framing, DPTx 1.4 IP core

DisplayPort 1.4 compatible. ; Ultra-small footprint (1k LUT minimum, 3.5k LUT maximum). ; Hardware proven on AMD/Xilinx 28nm FPGA fabric. ; Ships with an example project which demonstrates the ...

2037
SECURE ENCLAVE IP

The TESIC-410 IP is a Common Criteria (CC) EAL5+ PP0084/PP0117 certification ready Secure Enclave available as a hard-macro for plug-and-play SoC integration. The TESIC-410 Secure Enclave ...

2038
RISC-V Secure Enclave IP

The TESIC-510 Secure Enclave IP provides the highest levels of security for an SoC. Based on a secured RISC-V RV32IMCB processor core the Secure Enclave includes patented design techniques ...

2039
Secure Enclave IP

The TESIC-420 IP is a Common Criteria (CC) EAL5+ PP0117 certification ready Secure Enclave available as a hard-macro for plug and-play SoC integration. The TESIC-420 Secure Enclave IP provides ...

2040

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