130nm OTP Non Volatile Memory for Standard CMOS Logic Process
LPDDR5X Secondary/Slave (memory side!) PHY
This is a memory side (Slave-side) interface for AI processors and other ASICS seeking the latest high speed, low power LPDDR interface protocols for general purpose data transfer, while adhering to the well known and well defined LPDDR5X standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic processes. It is also suitable for a wide variety of memories such as DRAM, SRAM as well as emerging memories including non-volatile memories, with appropriate modifications.
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