MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
You are here:
1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop
180TSMC_PLL_10 is designed to generate a high frequency signal in a range from 1GHz to 3GHz and a low frequency clock signal in a range from 6MHz to 100MHz. The frequency synthesizer consists of a voltage controlled oscillator (VCO) with an internal LC-circuit; system of programmable feedback dividers; digital frequency-phase detector (FPD); precision charge pumping system (CP) with built-in loop filter; programmable frequency divider of the reference signal; delta-sigma modulator (DSM); a system of comparators for automatic selection of the VCO subrange and power management unit (PMU). The PMU performs the function of a voltage regulator with the ability to select the maximum output voltage for indicating increased current consumption.
查看 1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop 详细介绍：
- 查看 1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop 完整数据手册
- 联系 1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop 供应商
PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL
- Jitter Cleaner PLL Digital Loop Filter
- TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL