High quality, low latency, secure video encoder for the transmission of HD video
HBM3 PHY IP on TSMC N5
The configurable Synopsys HBM3 PHY is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated application- specific HBM3 I/Os required for HBM3 signaling. The design is optimized for high performance, low latency, low area, low power, and ease of integration.
The hard macrocells are easily assembled into a complete 1024-bit HBM3 PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configurations registers
and BIST control. The HBM3 PHY includes a DFI 5.0-compatible interface to the memory controller, supporting DFI 1:1:2 and DFI 1:2:4 clock ratios. The design is compatible with both metal-insulator-metal (MIM) and non-MIM power decoupling strategies. Synopsys also offers a pre-hardened “drop-in” version of the Synopsys HBM3 PHY for customers that do not have significant custom requirements. For customers that require a custom hard Synopsys HBM3 PHY, Synopsys also offer PHY hardening design services.
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