samsung IP core / Semiconductor IP / Silicon IP

Home
搜索IP
验证 IP
业界新闻
白皮书
微博
视频
Slides
活动

≡ Menu Design And Reuse

现在登录
|
Subscribe

About D&R
|
D&R Enterprise Platform
|
dr-embedded.com
|
English Chinese

|
Login
|
Subscribe to D&R SoC News Alert

Design And Reuse

搜索IP
业界新闻
- Categories
- Latest News
  - intoPIX 和 Nextera-Adeas 在ISE 2025 上发布了在紧凑型 FPGA 上采用JPEG XS 的最新 IPMX 演示设计
    Wednesday Jan. 29, 2025
  - Andes晶心宣布推出 AndesCore® AX66 支持 RVA23、Multi-Cluster架构、虚拟机以及 Android 系统
    Thursday Jan. 23, 2025
  - 芯原与新基讯联合推出云豹系列第二代5G RedCap/4G LTE双模调制解调器IP
    Thursday Jan. 23, 2025
白皮书
- Categories
- Featured Articles
  - Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
    Wednesday Jan. 29, 2025
  - SoC design: What's next for NoCs?
    Monday Jan. 27, 2025
  - How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
    Monday Jan. 27, 2025
博客
- 微博
  - The Cyber Resilience Act and its Impact on Embedded Systems
    KiviCore Blog -
  - How JESD204 Self-Synchronizing Receiver works: An in-depth look
    Chip Interfaces Blog - Piotr Koziuk, Chip Interfaces
  - Revolutionizing Power Efficiency in PCIe 6.x: L0p and Flit Mode in Action
    Rambus Blog - Julien Eydoux, Rambus
视频
Slides
活动
- IP-SOC 2021 Archives

Choose a filter
- Full Site Search
- Silicon IP
- Verification IP
- Software IP
- News
- Industry Articles

You are here:

Silicon IP Catalog >
samsung
> Page 2

Search for Silicon IP

Refine your search >>

Narrow your Selection

Refine by ASIC Foundry

Fujitsu

40nm
45nm

GLOBALFOUNDRIES

12nm
130nm
14nm
180nm
20nm
22nm
28nm
32nm
40nm
55nm
65nm
90nm

HHGrace

180nm

HLMC - Huali

28nm
40nm
55nm

Intel Foundry

16nm

Jazz

130nm
180nm

Renesas

90nm

SMIC

110nm
130nm
14nm
150nm
153nm
160nm
180nm
250nm
28nm
40nm
55nm
65nm
90nm

Samsung

4nm
5nm
7nm
8nm
10nm
11nm
14nm
28nm
32nm
45nm
65nm
90nm

TSMC

3nm
4nm
5nm
6nm
7nm
10nm
110nm
12nm
130nm
150nm
160nm
16nm
180nm
20nm
22nm
28nm
40nm
45nm
55nm
65nm
80nm
85nm
90nm

Tower

130nm
180nm
500nm

UMC

110nm
130nm
14nm
150nm
162nm
22nm
28nm
40nm
55nm
65nm
80nm
90nm

Refine by Provider

To get full access, please login here.

You must be registered with the D&R website to view the full search results, including:

Complete datasheets for samsung products
Contact information for samsung Suppliers

Please log in here to your account.

New user ? Signup here.

Samsung IP Listing

518 IP Cores (81 - 120)

找不到我需要的：
搜索特定的IP？点击此处

High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP for 5G, WiFi, etc

Perceptia’s DeepSub™ pPLL08F is an high performance RF frequency synthesizer PLL featuring industry leading jitter (sub 300fs), phase noise and compact area suitable for RF applications, ...

81
High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc

Perceptia’s DeepSub™ pPLL08F is an high performance RF frequency synthesizer PLL featuring industry leading jitter (sub 300fs), phase noise and compact area suitable for RF applications, ...

82
MIPI D-PHY Universal IP in Samsung 28FDSOI

The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 v1.2 ...

1 Testimonial
Gordon Hands, Director of Product Marketing, Lattice Semiconductor

83
OTP One Time Programmable IP Samsung 90CIS

Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The required voltage for OTP bit cell programming can ...

84
1.8V/3.3V Switchable GPIO With 5V I2C Open - Drain & Analog Cells in Samsung 11nm LPP

SAMSUNG 11nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBUS open-drain cell, 5V OTP cell, 1.8V & 3.3V analog cells, and associated ...

85
Dual channel 12-bit, 1GS/s ADC in Samsung 8nm for 5G & WIFI6

ADIQ12B1G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 1GS/s. This ADC samples wide bandwidth analog signals with good linearity best suited for many applications. ...

86
14b, 2Gsps, Self-Calibrating Current Steering IQDAC in samsung 8nm for 5G & WIFI6

DAIQ14CS2G08NLL is high performance 14b current steering IQDAC that supports data rate up-to 2Gsps. Each DAC core consists of a current source matrix with quad switching architecture, controlled ...

87
Dual channel 12-bit, 4GS/s ADC IP for 5G in 8nm process

ADIQ12B4G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 4.0 GS/s. This ADC samples wide bandwidth analog signals with good linearity best suited for many ...

88
14b, 4Gsps, Self-Calibrating Current Steering IQ DAC for 5G & WIFI6 in samsung 8nm

DAIQ14CS4G08NLL is high performance 14b current steering IQDAC that supports data rate up-to 4Gsps. Each DAC core consists of a current source matrix with quad switching architecture, controlled ...

89
Low-voltage detector designed in Samsung Foundries 65nm LFR6LP process node

Low-voltage detector designed in Samsung Foundries 65nm LFR6LP process node to monitor its own AVD supply and generate information to the SoC in case AVD falls under a certain threshold.

90
Low-power capacitor-less LDO with embedded voltage reference designed in Samsung Foundries LF6RLP process

The caplessLDO-ref-[1.8-5.5]-[0.9-1.4].01 is a capacitor-less Linear Regulator with programmable output voltage, used to generate SoC internal voltage supply from a Li-Ion battery, coin cell, ...

91
Low-power capacitor-less LDO designed in Samsung Foundries LF6RLP process

The caplessLDO-ref-[1.8-5.5]-[0.9-1.4].01 is a capacitor-less Linear Regulator with programmable output voltage, used to generate SoC internal voltage supply from a Li-Ion battery, coin cell, ...

92
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL

The Clock generator PLL is designed to multiply an input clock signal by an integer 40 and 50. It does not provide any de-skew functionality . The output is 2.5GHz with 50% duty cycle with quadrature ...

93
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process

TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features ...

94
High Speed Low Jitter 16GHz Output LC PLL

Terminus Circuits offers an Analog Phase Locked Loop which is a LC oscillator-based integer-N PLL IP powered at 900 mV. The PLL operates with input reference frequency of 100 MHz makes it applicable ...

95
I3C Master / Slave Controller - MIPI Basic v1.0

The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC v1.0 Improved Inter Integrated Circuit ...

96
12-bit SAR ADC Samsung

The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up ...

97
Programmable Threshold Analog Comparator on Samsung

agileCMP GP – Programmable-Threshold Comparator The agileCMP GP programmable-threshold comparator features a user-selectable (enable/disable) hysteresis as well as programmable threshold ...

98
8-10 bit SAR ADC Samsung

The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 10-bit resolution at sample rates up ...

99
8-10 bit DAC Samsung

The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC uses its own internal reference voltage. The architecture can achieve up to ...

100
Linear LDO Low-Dropout Voltage Regulator Samsung

The agileLDO is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture ...

101
Power-On-Reset Samsung

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

102
Bandgap Voltage / Current Reference Samsung

The agileBandGapGP consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of ...

103
Temperature Sensor Samsung

The agileTSENSE_A is a GP temperature sensor, a traditional ΔVBE temperature sensor that amplifies the difference between two VBE voltages, and converts the result to a single-ended signal. ...

104
Voltage Glitch Sensor Samsung

The agileVGLITCH voltage monitor provides security and protection against voltage side-channel attacks (SCA) and tampering such as supply voltage changes/glitches and power supply manipulation. ...

105
RC Oscillator Samsung

The agileOSC RC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of process variation. This can also be configured as a Free Running ...

106
IR DROP Samsung

The agileIRDROP I-R Drop Sensor is a circuit to detect supply I-R drops within the system. It is useful to detect loss of power or attacks to the power supply. The agileIRDROP consists of ...

107
Digital Cell Library Samsung

The agileDSCL is a compact digital standard cell library customisable for specific foundries and processes, and optimised for low-power, ultra-low-leakage, high-density or high-speed applications. ...

108
3.3V to 1.8V, 0.7A Step-down DC-DC converter

High-efficiency step-down DC-DC converter is targeted for operation from 3.3V input voltage. It is able to supply circuits with programmable output voltage 1.8V at 0.7A output current. The DC-DC ...

109
3.3V to 1.0V, 3.0A Step-down DC-DC converter

High-efficiency step-down DC-DC converter is targeted for operation from 3.3V input voltage. It is able to supply circuits with programmable output voltage 1.0V at 3A output current. The DC-DC ...

110
30mA 2-channel LDO voltage regulator (output voltage each channel 1.0V)

028SAM_LDO_04 is external-capacitor-based Linear Regulator in Samsung 28 FD-SOI to generate SoC voltage supply voltage. It contains two independently programmable drivers to generate stable ...

111
Samsung 28nm FDSOI 1.8v/1.0v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] and DN [11:0] to different values according ...

112
Samsung 28nm FDSOI 1.8v/1.0v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] and DN [11:0] to different values according ...

113
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY

The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit parallel ...

114
Samsung 28nm FDSOI Codec

The SEC28FDSOI18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PLL to support a wide range of sample rates. ...

115
103 dB of SNR, 24-bit stereo multichannel audio CODEC with capless headphone outputs, suitable for 5.1 applications

SNR performance and integration issues make System designers reluctant to consider integrating audio Codec IP in applications like PC sound card and DVD player where high definition audio is ...

116
HSIC PHY

The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy USB overhead, this PHY is the size of a few ...

117
RapidIO 2.0 PHY & Controller

The Innosilicon Serdes Combo PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for RapidIO. The PHY supports the RapidIO ...

118
SATA 3.0 PHY

The INNOSILICON mixed signal SATA3.0 transceiver PHY provides a complete SATA3.0 standard compliant transceiver physical interface solution for delivering high speed data over point to point ...

119
XAUI PHY

The Innosilicon XAUI PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 standard. The PHY supports XAUI physical layer specifications. ...

120

Previous Page | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | Next Page

IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Silicon IP catalog (6 500 products from more than 400 companies)

EETimes

本网站的任何部分未经Design&Reuse许可，不得复制，重发，转载或以其他方式使用。

业务合作

访问我们的合作伙伴页面了解更多信息

成为合作伙伴

添加产品

供应商免费录入产品信息

公布产品信息

Design-Reuse.com

意见反馈
关于我们
合作伙伴
Advertise with Us
隐私政策