This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] and DN [11:0] to different values according to different REFIN, CLK_VCO will be locked at the multiples of input frequency.CLKO is CLK_VCO divided by DP[2:0].
- Process: Samsug 28nm FDSOI 1V/1.8V CMOS process
- Supply voltage: 0.9V<=VDDA<=1.1V, 0.9V<=VDD<=1.1V
- Mos device type: nfet, pfet
- Operating current: VDDA<1.2mA(1GHz) AVDD<6mA(3.2GHz)
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C