Dual channel 12-bit, 4GS/s ADC IP for 5G in 8nm process
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A/D IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- 12-bit 50/100MSPS SAR A/D Converter in 55nm LL
- 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- 2D/3D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- 3D OpenGL ES GPU (Graphics Processing Unit)
- JESD204D