PCIe Gen 6 SerDes IP - up 112G LR ethernet
Support 7nm and 6nm foundry process at leading foundry
Available for design in now
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112G IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
- DesignWare 112G Ethernet PHY IP for TSMC N7 Process
- DesignWare 112G Ethernet PHY IP in TSMC N5
- DesignWare 112G Ethernet PHY IP for TSMC N7 Process
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency