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12-bit 212MS/s Pipeline ADC
The 12-bit 212MS/s Pipeline ADC is a low-power ADC that is re-configurable as a Single Time-Interleaved ADC with sampling rate of 212MS/s or as a Dual Input ADC with sampling rate of 106MS/s per channel.
特色
- TSMC 65nm CMOS LP Logic Process
- 1.2V and 2.5V Power Supply
- Re-Configurable to be a:
- Single 12-Bit Time-Interleaved ADC operating at up to FS=212MS/s (IF Mode)
- Dual 12-Bit ADC operating at up to FS=106MS/s per channel (BB Mode)
- 1Vpp Differential Input Range
- DC Linearity:
- IF Mode: DNL ±0.75LSB; INL ±3.0LSB
- BB Mode: DNL ±0.5LSB; INL ±2.5LSB
- Low Power Dissipation
- SNR @ FIN = 10MHz (Typical)
- IF Mode: 64dB
- BB Mode: 67dB
- SNDR @ FIN = 10MHz (Typical)
- IF Mode: 63dB; 10.2 ENOB
- BB Mode: 65dB; 10.5 ENOB
- SFDR @ FIN = 10MHz (Typical)
- IF Mode: 70dB
- BB Mode: 73dB
- Stand-By and Power Down Modes
- Compact Die Area
可交付内容
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
应用
- Mobile Communications: HSPA, LTE
- WiFi, WiMax
- Powerline Communications
- DOCSIS, MoCA, DVB-C
Block Diagram of the 12-bit 212MS/s Pipeline ADC
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