MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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12-bit 1-channel 15 to 25 MSPS pipeline ADC
250iHP_ADC_03 is a low-power high-speed 12-bit ADC that employs high-performance differential pipeline architecture. The block consists of a sample and hold device, a core ADC and block of comparators. The ADC requires: 2.5 V analog supply, differential reference voltages 1.5 V and 1.0 V, common mode voltage 1.25 V and differential input clock. The ADC supports standby mode which allows state with minimum power consumption. There is also the ability to configure the operating modes of the ADC by using digital registers.
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12-bit ADC analog-to-digital converter IP
- This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
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