Adaptive Data Processing SoC
Active power management allows for mobile and static applications. Secure dedicated subsystem for communications and data management allows for commercial, industrial, and secure applications
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Block Diagram of the Adaptive Data Processing SoC
ASIC IP
- ReRAM NVM in 130nm CMOS, S130
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
- Ethernet 10/100 PHY
- USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF