65nm FTP Non Volatile Memory for Standard CMOS Logic Process
You are here:
USB 2.0 PHY TSMC 28HPM
The USB 2.0 PHY IP is designed to the USB 2.0 specification, and operates at High Speed (480Mbps), and Full Speed (12Mbps), and Low Speed (1.5Mbps). It complies with the UTMI v1.05 specification. The Cadence 2.0 PHY IP also supports USB Battery Charging Specification, Revision 1.2.
Implemented on the TSMC 28HPM process, the Cadence USB 2.0 PHY IP provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that not only meet, but exceed the requirements of high-performance designs and mplementations.
Implemented on the TSMC 28HPM process, the Cadence USB 2.0 PHY IP provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that not only meet, but exceed the requirements of high-performance designs and mplementations.
查看 USB 2.0 PHY TSMC 28HPM 详细介绍：
- 查看 USB 2.0 PHY TSMC 28HPM 完整数据手册
- 联系 USB 2.0 PHY TSMC 28HPM 供应商
USB IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm)