400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
eUSB 2.0 PHY in TSMC (N5, N4P, N3E, N3P)
The Synopsys eUSB2 IP is built on years of customer successes with Synopsys’ silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm.
With over 3,000 design wins and over 4 billion silicon-proven units shipped, Synopsys' USB IP solution, consisting of digital controllers, PHYs, IP subsystems, and verification IP, enables designers to lower integration risk and speed time-to-market.
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