Ultra Low Power MP3 Decoder

特色

• All MP3 decoding functions implemented at RTL level
• Smallest size (45 K gates plus 13 Kbytes data RAM)
• Lowest power consumption (clock required 9 MHz)
• Single clock synchronous design
• Support both ISO11172-3 and ISO13818-3 layer III audio decoding
• Straightforward interfaces for SoC applications
• Fully synthesizable technology independent of verilog RTL code
• Ten-bands equalizer with 64 steps for -20 to 20 dB gain
• Thirty-two steps volume control

可交付内容

• Synthesizable verilog source code
• Verilog testbench

Block Diagram of the Ultra Low Power MP3 Decoder

• 查看 Ultra Low Power MP3 Decoder 完整数据手册
• 联系 Ultra Low Power MP3 Decoder 供应商