DSC Decoder
Compliant with the VESA DSC 1.2a and 1.2b standards, CYBDSC2d IP core supports various coding schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB. It performs visually lossless compression, low gate count and latency for ultra-high definition display applications. It can be fastly and easily integrated into ASIC and FPGA applications for 4K / UHD TV, DisplayPort 1.4, USB Type-C device and AR / VR product.
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Block Diagram of the DSC Decoder
DSC IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs