PCIe Gen 2.0 PHY - FlipChip - TSMC 28HPC

The Cadence PHY IP for PCIe Gen2 is a hard PHY macro consisting of a Physical Media Attachment (PMA) layer and a soft Physical Coding Sublayer (PCS). The Cadence PHY IP for PCIe Gen2 is designed to the PCIe 2.0 specification, and operates at 5.0GTps and 2.5GTps. The PCS complies with the PIPE 3.0 (v0.9) specification, and provides support for the dynamic equalization features of PCIe Gen2. Cadence design-in kits provide flexibility in board design.

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