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PCIE 3.0 PHY UMC 28HPC+
The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
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PCIE 3.0 PHY IP
- Rambus PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon Proven in SAMSUNG 8LPP
- Rambus PCIe 5.0 Customizable Embedded Multi-port Switch
- Rambus PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- Rambus PCIe 5.0 Controller with AMBA AXI interface
- Rambus PCIe 5.0 SerDes PHY