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MIPI IP Core

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MIPI IP Listing

570 IP Cores (81 - 120)

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I3C Host Controller v1.2

The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between ...

81
MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5

The MXL-CDPHY-DSI-TX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY can ...

82
MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX

The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured ...

83
UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0

The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass storage devices. The UFS uses UniPro as the ...

84
MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7

The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHYv2.5 and C-PHYv2.0. The PHY ...

85
MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM

The MXL-DPHY-CSI-2-RX+ is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave ...

1 Testimonial
Nadav Katsir, General Manager, Lumissil

86
MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP

The MXL-D-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as ...

87
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP

The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY can ...

88
High Performance Second Generation Extended MIPI CSI2 Receiver

Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth between the camera and the application processor. ...

89
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock

The Extended MIPI CSI2 Serial Video Receiver IP core is designed to support those trends, and, at the same time, work with a relatively slow clock rate, processing several pixels per clock. ...

90
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2

The Multiplexing MIPI CSI2 Transmitter supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream

91
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter

The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of the SVTPlus2500 allows relatively slow internal ...

92
MIPI DSI TX Controller

The MIPI DSI Transmitter IP is an all-digital design consisting of a Redistribution Layer to interface to one or more Display Modules, external register interface for configuration of the Transmitter ...

93
MIPI CSI-2 RX Controller for v2.1

CSI-2 receiver controller for application processor The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is responsible for handling and decoding ...

94
Controller for MIPI Soundwire

Integration functionality is the phrase for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and ...

95
MIPI CSI-2 TX Controller for v2.1

CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance Specification for Display Serial ...

96
I3C Controller

Controller IP for the MIPI I3C interface The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required for today’s ...

97
MIPI D-PHY for TSMC

D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, the PHY IP is silicon-proven and ...

98
MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP

The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0 The PHY can ...

99
MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables

Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading ...

100
MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 28HPC+

The MXL-DPHY-CSI-2-TX+-T028HPC+-RF-ULL is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible ...

1 Testimonial
Jim Hall, Vice President of Hardware, Perceive

101
MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX

The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with ...

1 Testimonial
Jim Hall, Vice President of Hardward, Perceive

102
MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP

The MXL-DPHY-CSI-2-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured ...

103
MIPI D-PHY CSI-2 RX+ IP in TSMC 28HPC+ for Automotive Applications

The MXL-DPHY-CSI-RX+-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured ...

104
MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm

The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI ...

1 Testimonial
Arnaud Foucher, Marketing Director, Teledyne e2v

105
MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm

The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The ...

106
I3C V1.1 Advanced Controller

I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to support modern mobil...

107
I3C V1.1 Autonomous Target

The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to process the data. Instead, data is...

108
I3C V1.1 Advanced Target

The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to any device. It ca...

109
I3C Lite Advanced Controller

The I3C Advanced Controller Lite is a highly configurable I3C controller that can be used in microcontroller-based environments to provide I3C connectivity to any ...

110
I3C Lite Advanced Target

The I3C Advanced Target Lite is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to any device. ...

111
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps

The MXL-CDPHY-4p5G-CSI-2-TX+-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.1. The ...

112
MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm, N7) for Automotive

Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence ...

113
MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm, N7) for Automotive

Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence ...

114
MIPI D-PHY Tx IP，在 TSMC 7FF 中经过硅验证

低功耗C-PHY/D-PHY 组合在各种制造节点生产成本低廉。用户可以根据应用需求选择将这个组合PHY IP设置为D-PHY 或C-PHY模式。此外，这个PHY IP还支持 PPI 接口，能够与 CIS-2 或 DSI...

115
MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 40LP

The MXL-DPHY-CSI-2-RX+-T-040LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY. The IP is configured as a MIPI ...

1 Testimonial
Nadav Katsir, General Manager, Lumissil

116
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP

The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v1.2. The PHY ...

117
MIPI D-PHY Receiver for TSMC 40nm LP

The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process.

118
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI

The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process.

119
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP

The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process.

120

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