MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
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MIPI D-PHY for TSMC
D-PHY physical layer
Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, the PHY IP is silicon-proven and shipping in high volume in multiple mobile devices.
Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, the PHY IP is silicon-proven and shipping in high volume in multiple mobile devices.
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