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Memory & Logic Library
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Memory & Logic Library IP Core

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Memory & Logic Library IP Listing

5132 IP Cores (1961 - 2000)

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搜索特定的IP？点击此处

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1961
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

1962
1963
UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

1964
UMC 0.11um CIS Process cell library

UMC 0.11um CIS Process cell library

1965
UMC 0.11um AL/LL Logic Process miniLib standard cell library

UMC 0.11um AL/LL Logic Process miniLib standard cell library

1966
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)

HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)

1967
UMC 0.18UM Mixed Mode/RF; Two Port Register File

UMC 0.18UM Mixed Mode/RF; Two Port Register File

1968
Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

1969
65nm Channel Length - Ultra High Density 7 - track Standard Cell library - TSMC 55NM 55LP (CLN55LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1970
70nm Channel Length - High Performance & High Density 10 - track Standard Cell library - TSMC 55NM 55LP (CLN55LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1971
70nm Channel Length - Ultra High Density 6 - track Standard Cell library - TSMC 55NM 55LP (CLN55LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1972
70nm Channel Length - Ultra High Density 7 - track Standard Cell library - TSMC 55NM 55LP (CLN55LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1973
DDRx & LPDDRx I/O TSMC 16nm 16FFC

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1974
DDRx & LPDDRx I/O TSMC 16nm 16FFP

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1975
High Performance & High Density 10 - track Standard Cell library - TSMC 018um G (CL018G)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 800 fully customizable ...

1976
High Performance & High Density 10 - track Standard Cell library - TSMC 180NM 180LP (CLN80LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 800 fully customizable ...

1977
High Performance & High Density 10 - track Standard Cell library - TSMC 80NM 80LP (CLN80LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 800 fully customizable ...

1978
I2C - TSMC 12nm 12FFC

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1979
I2C - TSMC 16nm 16FFC

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1980
I2C - TSMC 16nm 16FFP

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1981
Embedded OTP (One-Time Programmable) IP, 1.2V/6V/32V HV

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1982
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1983
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1984
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1985
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1986
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1987
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1988
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1989
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1990
Embedded OTP (One-Time Programmable) IP, 1.5V/6V/32V MTE

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1991
Embedded OTP (One-Time Programmable) IP, 1.5V/5V LP

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1992
Embedded OTP (One-Time Programmable) IP, 1.5V/5V BCD

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1993
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1994
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1995
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1996
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (5V) LP EEPROM process. The write ...

1997
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (6V) LP EEPROM process. The write ...

1998
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (7V) LP EEPROM process. The write ...

1999
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (8V) LP EEPROM process. The write ...

2000

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