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Memory & Logic Library
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Memory & Logic Library IP Core

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Memory & Logic Library IP Listing

5123 IP Cores (1961 - 2000)

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1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1961
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

1962
1963
UMC 0.11um CIS Process cell library

UMC 0.11um CIS Process cell library

1964
UMC 0.11um AL/LL Logic Process miniLib standard cell library

UMC 0.11um AL/LL Logic Process miniLib standard cell library

1965
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)

HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)

1966
Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

1967
Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

1968
28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V

28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V

1969
70nm Channel Length - High Performance & High Density 10 - track Standard Cell library - TSMC 55NM 55LP / LP_eF / ULP / ULP_eF / GP

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1970
70nm Channel Length - Ultra High Density 6 - track Standard Cell library - TSMC 55NM 55LP / LP_eF / ULP / ULP_eF / GP

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1971
70nm Channel Length - Ultra High Density 7 - track Standard Cell library - TSMC 55NM 55LP / LP_eF / ULP / ULP_eF / GP

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable ...

1972
DDRx & LPDDRx I/O TSMC 16nm 16FFC

Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

1973
SD/eMMC I/O

SD (Security Digital) and eMMC (embedded MultiMedia Card) IOs are nonvolatile memory interface technology with high bandwidth capabilities, which is particularly developed for flash storage ...

1974
Embedded OTP (One-Time Programmable) IP, 1.2V/6V/+-16V HV

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1975
Embedded OTP (One-Time Programmable) IP, 1.8V/5V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1976
Embedded OTP (One-Time Programmable) IP, 1.8V/5V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1977
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1978
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1979
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1980
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1981
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1982
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1983
Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V Logic

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1984
Embedded OTP (One-Time Programmable) IP, 1.5V/6V/32V MTE

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1985
Embedded OTP (One-Time Programmable) IP, 1.5V/5V LP

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1986
Embedded OTP (One-Time Programmable) IP, 1.5V/5V BCD

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1987
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1988
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1989
Embedded OTP (One-Time Programmable) IP, 3.3V Green

eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated ...

1990
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (5V) LP EEPROM process. The write ...

1991
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (6V) LP EEPROM process. The write ...

1992
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (7V) LP EEPROM process. The write ...

1993
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (8V) LP EEPROM process. The write ...

1994
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V 10V) LP EEPROM process. The write ...

1995
Embedded EEPROM IP, 1.8V/3.3V/5V EEPROM

eMemory's EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V 11V) LP EEPROM process. The write ...

1996
MCU PAD - SMIC 55nm Eflash

1.8V/3.3V/1.2V power supply can be used;  Including ultra-low leakage MCU I/O total solution;  Supports 1.2V core voltage power off, and get ultra-low leakage;  Provides a wide variety ...

1997
PAD - SMIC 110nm generic

Standard I/O size is low to 78um*32um; HBM ESD: ±2000V; MM: ±200V; CDM: ±500V; LU: 150mA

1998
MCU PAD - SMIC 55nm Eflash

Supports 1.2V off with 3.3V/2.5V latches ; Low power crystal oscillator amplifier, the current of 32.768KHz crystal is lower than 200nA ; Standard I/O size is low to 70um*128um ; HBM ESD: >2000V; ...

1999
16K8 MTP

XRX018BCDMTP_16K8A is a BCD compatible embedded non-volatile memory IP with 16k8 ROM density. This IP could be used for code storage, firmware update, parameter setting, trimming and calibration, ...

2000

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