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Silicon IP Catalog
Memory & Logic Library
> Page 49

Memory & Logic Library IP Core

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Memory & Logic Library IP Listing

5255 IP Cores (1961 - 2000)

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UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.

1961
UMC 0.18UM Mixed Mode/RF; Two Port Register File

UMC 0.18UM Mixed Mode/RF; Two Port Register File

1962
55 SP Dual Port SRAM compiler with 1P4M metal option

55 SP Dual Port SRAM compiler with 1P4M metal option

1963
UMC 55nm EFLASH Process Two Port Register File

UMC 55nm EFLASH Process Two Port Register File

1964
UMC 55nm eflash process , Two Port Register File memory compiler

UMC 55nm eflash process , Two Port Register File memory compiler

1965
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

1966
40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature

40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature

1967
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail

UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail

1968
UMC 28nm HPC process Dual Port SRAM compiler

UMC 28nm HPC process Dual Port SRAM compiler

1969
UMC 28nm HPC process Two Port Register File

UMC 28nm HPC process Two Port Register File

1970
UMC 28nm HPC process 2PRF with Bank2

UMC 28nm HPC process 2PRF with Bank2

1971
UMC 28nm HPC process Two Port Register File with Bank2

UMC 28nm HPC process Two Port Register File with Bank2

1972
UMC 28nm HPC process Two Port Register File with peri LVT

UMC 28nm HPC process Two Port Register File with peri LVT

1973
UMC 28nm HPC process Two Port Register File with LVT and Bank2

UMC 28nm HPC process Two Port Register File with LVT and Bank2

1974
UMC 28nm HPC process Two Port Register File with LVT and Bank4

UMC 28nm HPC process Two Port Register File with LVT and Bank4

1975
UMC 28nm HPC process PG Two Port Register File

UMC 28nm HPC process PG Two Port Register File

1976
UMC 28nm HPC process 2PRF with Bank2 & power gating

UMC 28nm HPC process 2PRF with Bank2 & power gating

1977
UMC 28nm HPC process PG-2PRF with Bank4

UMC 28nm HPC process PG-2PRF with Bank4

1978
UMC 28nm HPC process PG Two Port Register File with peri-HVT

UMC 28nm HPC process PG Two Port Register File with peri-HVT

1979
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.

1980
Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

1981
Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

1982
Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

1983
Ultra High Density and Ultra Low Power 7-track Standard cell library - TSMC 0.25um G (CL025G)

Dolphin s extensive array of Standard Cell libraries have been methodically tested and verified in silicon for each process technology supported. Each one of over 700 fully custom cells is optimized ...

1984
Ultra Low Power & Ultra High Density 7 - track Standard Cell library - TSMC 80NM 80LP (CLN80LP)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 800 fully customizable ...

1985
Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process FF+GL/FF+LL/FFC

Specialty Memory Solutions

1986
Ultra Low Leakage/Ultra Low Power Ternary-CAM/Binary-CAM, supports process ULL/ULP

Specialty Memory Solutions

1987
Ultra Low Leakage/Ultra Low Power Dual Port SRAM Compiler with Row/Column Redundancy Option, with write assist, supports process ULL/ULP

Memory Compilers

1988
Ultra Low Leakage/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with read assist, write assist, supports process ULL/ULP

Memory Compilers

1989
Ultra Low Leakage/Ultra Low Power Single Port Multi-banks SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, read assist, write assist, supports process ULL/ULP

Memory Compilers

1990
Ultra Low Leakage/Ultra Low Power One Port Register File (1 Port RF) Compiler with Column Redundancy Option, with write assist, supports process ULL/ULP

Memory Compilers

1991
Ultra Low Leakage/Ultra Low Power 2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with write assist, supports process ULL/ULP

Memory Compilers

1992
Ultra Low Leakage/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process ULL/ULP

Specialty Memory Solutions

1993
High Performance/Low Power/Ultra Low Power Ternary-CAM/Binary-CAM, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP

Specialty Memory Solutions

1994
High Performance/Low Power/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with read assist, write assist, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP

Memory Compilers

1995
High Performance/Low Power/Ultra Low Power Single Port Multi-banks SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, read assist, write assist, supports process HP/

Memory Compilers

1996
High Performance/Low Power/Ultra Low Power One Port Register File (1 Port RF) Compiler with Column Redundancy Option, with write assist, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP

Memory Compilers

1997
High Performance/Low Power/Ultra Low Power 2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with write assist, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP

Memory Compilers

1998
High Performance/Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP

Specialty Memory Solutions

1999
Low Power/Ultra Low Power Ternary-CAM/Binary-CAM, supports process G/LP/LP_eDRAM/ULP/ULPEF

Specialty Memory Solutions

2000

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