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Silicon IP Catalog
Memory Controller & PHY
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Memory Controller & PHY IP Core

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Memory Controller & PHY IP Listing

1051 IP Cores (121 - 160)

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HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard

Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates with the Synopsys HBM3 PHY IP via an extended ...

121
UHS-III PHY

Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC65 now.

122
Combo SerDes PHY

With sophisticated architecture and advanced technology, KNiulink multi-mode transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable ...

123
Slave side SPI/QPI controller 133MHZ

This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products. Max frequency hardware proven is 133MHz. Can be used for a variety of memory products and in-memory AI embedded ...

124
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology

IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology

125
TSMC CLN16FFGL+ HBM PHY IP

This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. The HBM PHY IP shall be an independent IP ...

126
TSMC CLN5FF HBM PHY IP

This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. The HBM PHY is compliant to the JEDEC HBM2E ...

127
TSMC CLN7FF HBM2E PHY IP

This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. The HBM PHY is compliant to the JEDEC HBM2E ...

128
AHB-Lite General Purpose Memory Module

The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defined in the AMBA 3 AHB-Lite v1.0 specifications ...

Try this IP for Free!

129
GDDR6 PHY IP for 12nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

130
HBM3 PHY IP at 7nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

131
LPDDR5X/5/4X/4 PHY IP for 12nm

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture ...

132
ONFI : Open NAND Flash Interface Host Controller

NAND Flash Interface controller that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design pre-association. The solution also provides ...

133
SD Memory Card Host Controller

VinSDHC3_0 SD Host Controller Core controls data transfers between the SD Host System and the SD Memory Card sockets. It is compliant with the standard SD Controller Specification version 3.0. ...

134
Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market

Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex interface protocols, the integration effort to ...

135
eMMC 4.51 Device Controller

The eMMC 4.51 Memory controller is compliant with the latest MMC 4.51 specification released by JEDEC. The controller provides a peak bandwidth of 104MB/s and supports all of the security features ...

1 Testimonial
David Moloney, Chief Technology Officer at Movidia, Movidia

136
SD 4.0 UHS-II PHY TSMC 28nm HPM North-South

The SD 4.0 UHS-II Analog PHY achieves a peak interface speed of 3.12 Gbps. The UHS-II PHY is compliant with the specification of UHS-II and is an extremely area and power efficient implementation. ...

137
SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller

The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: SD, SDIO and eMMC memory formats. This ...

138
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC-NS

Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core voltage of 1.1V and I/O voltage of 1.8/3.3V ...

139
SD 4.1 UHS-II PHY for TSMC 12nm FF

The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access ...

140
LPDDR5X/5/4X/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

141
Single-port 16/32/64-bit DDR266 Controller

The Single-port 16/32/64 bit DDR266 controller IP core is a DDR266 SDRAM controller AMBA AHB back-end. The controller can interface two 16-, 32- or 64-bit DDR266 memory banks to a 32-bit AHB ...

142
32/64-bit PC133 SDRAM Controller

The 32/64-bit PC133 SDRAM Controller” controller handles PC133 SDRAM compatible memory devices attached to a 32 or 64 bit wide data bus. The controller acts as a slave on the AHB bus where ...

143
32-bit SRAM/PROM Controller

The 8/32-bit PROM/SRAM Controller IP cores is an 8/32-bit PROM/SRAM/IO controller that interfaces external asynchronous SRAM, PROM and I/O to the AMBA AHB bus. The controller can handle 32-bit ...

144
32-bit SSRAM/PROM Controller

The 32-bit SSRAM/PROM Controller IP cores is an 32-bit SSRAM/PROM/IO controller that interfaces external Synchronous pipelined SRAM, PROM, and I/O to the AMBA AHB bus. The controller acts as ...

145
NAND Flash Memory Controller with DMA

NANDFCTRL2 is a VHDL IP core implementing an interface to NAND flash memory devices. The core supports ONFI 4.0 and provides DMA transfers to and from the memory. The core implements a BCH EDAC ...

146
DDR2 & DDR3 Fault Tolerant Memory Controller

FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance. On the memory side, it presents a DFI ...

147
QUAD SPI Memory controller

The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly accessing the memory using reads on a AHB ...

148
Frame Rate Converter for 4K

TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which generates high accuracy and non-artifact ...

149
DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC

With sophisticated architecture and advanced technology, this DDR3/4 and LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS process, KNiulink could offer both ...

150
DDR5/4 PHY & Controller

DDR5/4 PHY & Controller

151
LPDDR4/3, DDR4/3 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

152
GDDR6 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

153
High Performance HBM, HBM3 Memory Controller

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

154
DDR3/DDR4 IP solution with high performance and low power

With sophisticated architecture and advanced technology, KNiulink provide DDR3/DDR4 IP solution with high performance and low power. KNiulink could offer both controller and PHY IPs. The speed ...

155
DDR3/3L/DDR4/LPDDR4 PHY

The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-party DFI-compliant DDR3, DDR3L, DDR4, or ...

156
DDR4 PHY, 16nm/12nm

The DDR4 PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR4 memory controller. Depending on the loading ...

157
DDR5/4 COMBO PHY 7nm/6nm

The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR5/4 memory controller. Depending on the ...

158
DDR5/4 COMBO PHY U22

The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR5/4 memory controller. Depending on the ...

159
LPDDR5/4X COMBO PHY 7nm/6nm

The LPDDR5 and LPDDR4x Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant LPDDR5 and LPDDR4x memory controller. ...

160

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