High Performance HBM, HBM3 Memory Controller
OMC – HBM3 Memory Controller is a small & highly configurable IP. It provides high performance through advanced memory controller design based on a proprietary out-of-order scheduling algorithm and high-speed implementation technique. Demand for more DRAM bandwidth is getting stronger than ever in a quest to improve user experiences (e.g., higher image resolution). Given the limited amount of physically available DRAM bandwidth, highly efficient memory controller IP is becoming a very critical issue everywhere. With our OMC – HBM3 Memory Controller, SoCs can save significant amounts of area & power consumption and meet next-generation SoC’s DRAM bandwidth requirements.
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