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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Listing

1936 IP Cores (441 - 480)

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GSMC0.18um PCI I/O Cells DUP Library

VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P5M Salicide 1.8V/3.3V process. ...

441
GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library

VeriSilicon GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um logic 1P5M 2.5V/3.3V process. This ...

442
SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library

VeriSilicon SMIC 0.13um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um logic 1P8M 1.2V/3.3V process. ...

443
SMIC 0.18um PCI I/O Cells Library

VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8V/3.3V ...

444
Media Local Bus Interface

The Media Local Bus Interface IP core complies with the latest MLB Specification version 4.2, and works with all MOST network generations - MOST25, MOST50, and MOST150. It supports a 3-pin ...

445
Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane

Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12832M8R2JM3KIP2400 is designed to support data rate in excess of maximum 2.4Gbps utilizing SLVS-EC / sub-LVDS / CMOS 1.8V interface ...

446
Multi-PHY Receiver Link Controller

CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting ...

447
Gen4 PCIe to AXI Bridge (PAB)

The Gen3 PCIe to AXI Bridge is a highly flexible and configurable IP with a PCI Express* interface on one side and an AMBA AXI interface on the system side. The Bridge has been architectured ...

448
NVMe-to-SATA Bridge

The IntelliProp IPP-NV186A-BR is an NVMe-to-SATA Bridge that utilizes the IntelliProp NVMe Target IP Core and the IntelliProp SATA AHCI Host Core to create an NVMe-to-SATA protocol bridge. The ...

449
32-bit PCI Host Bridge

Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Efficient back-end interface for ...

450
64-bit PCI Bus Master/Target

Fully supports PCI specification 2.1 and 2.2 protocol. ; Supports both 64-bit and 32-bit bus systems. ; Supports dual address cycle (DAC) 64-bit addressing. ; Designed for ASIC and PLD implementations. ...

451
64-bit PCI Bus Target

Fully supports PCI specification 2.1 and 2.2 protocol. ; Supports both 64-bit and 32-bit bus systems. ; Supports dual address cycle (DAC) 64-bit addressing. ; Designed for ASIC and PLD implementations. ...

452
64-bit PCI Host Bridge

Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Supports both 64-bit and 32-bit bus systems. ; Fully static design with edge triggered ...

453
PCI Bus Arbiter

Compliant with PCI bus specification 2.2. ; Designed for ASIC and PLD implementations in various system environments. ; Fully static design with edge triggered flip-flops. ; Supports two ...

454
PCI-ISA Bridge

Compliant with PCI bus specification 2.1 and 2.2. ; Convert PCI transaction to ISA bus transaction. ; Function as PCI target on PCI bus. ; Function as ISA master on ISA bus. ; Map PCI address ...

455
PCI-to-PCI Bridge

Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Independent ...

456
AHB To PCI Wrapper

VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can also used to certify AHB based products ...

457
SATA Host Controller

The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. The LDS SATA HOST STR4GX IP is compliant with ...

458
Configurable AES Core with APB or AHB interface

eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a flexible trade-off of key size, modes and ...

459
SATA Host Controller on Spartan 6 LXT FPGA

The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is compliant with Serial ATA II specification ...

460
SATA III HOST Controller on Virtex 6

The SATA III HOST Controller IP Core incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The SATA III HOST Controller IP Core is compliant ...

461
SATA Host on Altera Arria II GX

The SATA Host IP Core incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The SATA Host IP Core is compliant with Serial ATA ...

462
SATA Device Controller on Altera Arria II GX

The SATA Device Controller IP Core incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The SATA Device Controller IP Core is ...

463
SATA HOST Controller on Cyclone IV GX

The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The LDS SATA HOST C4GX IP is compliant with ...

464
SATA Device on Stratix IV GX

The SATA Device IP Core incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. The SATA Device IP Core is compliant with Serial ...

465
SATA RECORDER ON VIRTEX 6

The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of the data to record. The data can be recorded ...

466
SATA Host 6G Controller on Kintex 7

The SATA Host 6G Controller IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The SATA Host 6G Controller IP is compliant with Serial ...

467
SATA 3 Host Controller on ZYNQ

The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST XZ7 IP is compliant with Serial ATA III ...

468
SATA Device Controller on Kintex 7

The SATA Device IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The SATA Device IP is compliant with Serial ATA III specification ...

469
ZYNQ SATA 3 AHCI Host Controller with Linux Driver

The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS_SATA 3 HOST AHCI XZ7 ...

470
SATA HOST 3 ON VIRTEX 7 GTH

The LDS SATA 3 HOST XV7H IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTH speed grade 2 FPGA. The LDS SATA 3 HOST XV7H IP is compliant with Serial ...

471
SATA HOST 3 ON KINTEX 7 Ultrascale

The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The LDS SATA 3 HOST XK7U IP is compliant with ...

472
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)

The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential ...

473
SATA 2 HOST ON CYCLONE 5 GX

The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The LDS SATA 2 HOST_C5GX IP is compliant with ...

474
SATA RECORDER ON VIRTEX 7 GTX

The LDS SATA RECORDER XV7X IP is a complete recorder sub-system IP. It can be configured according to the recording performance required and the quantity of the data to be recorded. ; ; - The ...

475
LDS SATA RECORDER ON ZYNQ

The LDS SATA RECORDER XZ7 IP is a complete recorder sub-system IP. It can be configured according to the recording performance required and the quantity of the data to be recorded. ; ; - The ...

476
LDS SATA RECORDER IP ON ARTIX 7

The LDS SATA RECORDER XA7 IP is a complete recorder sub-system IP. It can be configured according to the recording performance required and the quantity of the data to be recorded. ; ; - The ...

477
SATA 3 HOST IP on ARRIA 10 FPGA

The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The LDS-SATA3-HOST-A10GX IP is compliant with ...

478
SATA Host on Xilinx Zynq Artix 7

The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 HOST XA7 IP is compliant with Serial ATA ...

479
USB2.0 OTG PHY supporting UTMI+ level 3 interface - SMIC 40LL / 110G / 130G / 130EF

The OTG PHY supports up to UTMI+ level 3. The area and power is pretty minimal compared with other vendors. In order to minimize the power and area, innovative architecture and techniques are ...

480

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