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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Core

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Interface Controller & PHY IP Listing

1846 IP Cores (441 - 480)

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MIPI M-PHY Designed For GF 28nm

ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a ...

441
USB1.1 PHY

The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed in standard logic to interface with the ...

442
USB 1.1 PHY

The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB1.1 core with RCV, VM and VP. It is designed in standard logic to interface with ...

443
USB1.1 PHY

The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed in standard logic to interface with the ...

444
USB1.1 PHY

The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed in standard logic to interface with the ...

445
USB 1.1 PHY

The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed in standard logic to interface with the ...

446
GSMC 0.15um 1.2V/3.3V PCI I/O Cells

VeriSilicon GSMC 0.15um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.15um logic low voltage 1P7M 1.2V/3.3V ...

447
GSMC 0.18um PCI I/O Cells Library

VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P6M Salicide 1.8V/3.3V process. ...

448
GSMC0.18um PCI I/O Cells DUP Library

VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P5M Salicide 1.8V/3.3V process. ...

449
GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library

VeriSilicon GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um logic 1P5M 2.5V/3.3V process. This ...

450
SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library

VeriSilicon SMIC 0.13um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um logic 1P8M 1.2V/3.3V process. ...

451
SMIC 0.18um PCI I/O Cells Library

VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8V/3.3V ...

452
USB 1.1 PHY

The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM, and transfers data to USB1.1 core with RCV, VM and VP. It is designed in standard logic to interface with ...

453
SMIC 0.13um USB 1.1 PHY

The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives data via DP and DM and transfers data to USB1.1 ...

454
SMIC 65nm USB2.0 Dual Role PHY

The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit ...

455
DO-254 AXI Timebase Watchdog Timer 1.00a

Provides a 32-bit free-running timebase and watchdog timer.

456
DO-254 AXI Universal Asynchronous Receiver Transmitter (UART) 16550 1.00a

Connects through an AXI4-Lite interface and provides the controller interface for asynchronous serial data transfer.

457
DO-254 AXI Bridge For PCI Express 1.00a

An interface between the AXI4 and PCI Express®.

458
USB 2.0 PHY; SMIC 55nm LL

459
USB 2.0 PHY

SP-USB20PHY-T28HPCP is a USB 2.0 transceiver equipped with a wide spectrum of the host and peripheral functions and is fully compliant with the USB 2.0 specification. It is a complete transceiver ...

460
32-bit PCI Bus Master/Target

Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Efficient back-end interface for ...

461
32-bit PCI Bus Target

; Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Efficient back-end interface ...

462
32-bit PCI Host Bridge

Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Efficient back-end interface for ...

463
64-bit PCI Bus Master/Target

Fully supports PCI specification 2.1 and 2.2 protocol. ; Supports both 64-bit and 32-bit bus systems. ; Supports dual address cycle (DAC) 64-bit addressing. ; Designed for ASIC and PLD implementations. ...

464
64-bit PCI Bus Target

Fully supports PCI specification 2.1 and 2.2 protocol. ; Supports both 64-bit and 32-bit bus systems. ; Supports dual address cycle (DAC) 64-bit addressing. ; Designed for ASIC and PLD implementations. ...

465
64-bit PCI Host Bridge

Fully supports PCI specification 2.1 and 2.2 protocol. ; Designed for ASIC and PLD implementations. ; Supports both 64-bit and 32-bit bus systems. ; Fully static design with edge triggered ...

466
PCI Bus Arbiter

Compliant with PCI bus specification 2.2. ; Designed for ASIC and PLD implementations in various system environments. ; Fully static design with edge triggered flip-flops. ; Supports two ...

467
PCI-ISA Bridge

Compliant with PCI bus specification 2.1 and 2.2. ; Convert PCI transaction to ISA bus transaction. ; Function as PCI target on PCI bus. ; Function as ISA master on ISA bus. ; Map PCI address ...

468
PCI-to-PCI Bridge

Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1. ; Designed for ASIC and PLD implementations. ; Fully static design with edge triggered flip-flops. ; Independent ...

469
AMBA AHB Bus Master

Supports AHB bus interface to the ARM CPU. ; User interface designed for high speed access to any slave devices on the AHB Bus. ; User specified single or burst data access on the AHB interface ...

470
64-bit PCI-X Host Bridge

The EP423 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. The user interface is a highly efficient and flexible user interface which provides for easy ...

471
I2C MAster Slave

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using ...

472
I2C Master

The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt ...

473
I2C Slave

The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt ...

474
RSA public key cryptography APB peripheral

The standard RSA module is available as an eSi-RISC APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be configured for between 512 and ...

475
Complete High Voltage TCPC

CT20602_HVTCPC is a complete High Voltage Type-C Port Controller designed according to the TCPC Specifications. It perform, among other Specified TCPC functions, all required VBUS Monitoring ...

CT20602_EVB Evaluation System

476
USB-PD Complete Controller

CT20602_PDCTRL is a complete USB-PD Controller featuring both Port Controller and Port Manager functions in a single piece of silicon. The solution can be quickly and easily assembled around ...

CT20602_EVB Evaluation System

477
I2S/Left-Justified/TDM Digital Audio Interface

The AR38U12 is a soft macro IP supporting industry-standard I2S, Left-Justified and Time-Division-Multiplexed (TDM) serial interface to parallel PCM (pulse-code-modulation) data format conversion ...

478
USB2.0 OTG PHY supporting UTMI+ level 3 interface - SMIC 40LL / 110G / 130G / 130EF

The OTG PHY supports up to UTMI+ level 3. The area and power is pretty minimal compared with other vendors. In order to minimize the power and area, innovative architecture and techniques are ...

479
USB2.0 OTG PHY supporting UTMI+ level 3 interface - SMIC 28HK/55LL

The OTG PHY supports up to UTMI+ level 3. The area and power is pretty minimal compared with other vendors. In order to minimize the power and area, innovative architecture and techniques are ...

480

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