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I/O Library IP Listing

1404 IP Cores (321 - 360)

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MIPI D-PHY/LVDS Combo DSI RX (Receiver) in TSMC 110G

The MXL-DPHY-LVDS-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY and compatible with the TIA/EIA-644 ...

1 Testimonial
Yusuke Yamamoto, Senior Manager, Marketing & Strategic planning department, Kawasaki Microelectronics

321
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process

8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process.

322
LVDS Tx IO IP, UMC 90nm SP process

LVDS TX Pad, UMC 0.35um Logic process.

323
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process

2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.

324
LVDS Receiver IP, UMC 90nm SP process

DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.

325
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process

2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process.

326
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process

Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process.

327
LVDS Rx IO IP, UMC 0.18um Logic process

LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process.

328
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process

2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process.

329
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process

2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.

330
LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process

Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process.

331
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process

2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process.

332
Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps

The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess ...

333
1 Gbps DDR LVDS transmitter

065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other two internal pins (VREF_TX and IREF_TX) ...

334
1 Gbps DDR rail to rail LVDS receiver

LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data and the control pins (EN_RX, EN_RES) to configure ...

335
3.125 Gbps DDR CML receiver

065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD_INN are differential input pins that should ...

336
3.125 Gbps DDR 1-channel CML transmitter

065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter state and control pin EN_PR to toggle pre-emphasis ...

337
Up to 1.25 Gbps DDR LVDS IPs library

130TSMC_LVDS_04 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Bandgap reference block (LVDS_BG); • Bias blocks (LVDS_BIASRXnX, ...

338
Library of LVDS IOs cells for TSMC 40G

The nSIO2000_TS40G_2V5_0V9 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology. The library ...

339
TSMC 40G 2Gb/s RX LVDS IO cell

The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology.

340
TSMC 40G 2Gb/s TX LVDS IO cell

The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology.

341
TSMC 40G 2Gb/s bidirectional LVDS IO cell

The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology.

342
TSMC 40G Combo IO with 2Gb/s LVDS and CMOS GPIO

A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology. ...

343
Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)

PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps. PSI1250MP can provide interfaces for many applications operating from 9.5Gbps to 12.5Gbps. It also provides interfaces ...

344
Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and ...

345
Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and ...

346
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

347
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

348
Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew

V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source ...

349
FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz

V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source ...

350
FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability

V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display ...

351
Dual FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @120Hz) LVDS SerDes 10:70 channel decompression with deskew capability

This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined signals). ...

352
Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined ...

353
Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined ...

354
FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz (SVGA/WXGA/SXGA) LVDS SerDes 5:35 channel decompression

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals). ...

355
FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals). ...

356
FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals). ...

357
LVDS reference - TowerJazz 0.13um

LVDS reference

358
LVDS receiver - TowerJazz 0.13um

LVDS receiver

359
LVDS transmitter - TowerJazz 0.13um

LVDS transmitter

360

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