16bit 5Gsps silicon proven High performance Current Steering DAC IP Core
Dual FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @120Hz) LVDS SerDes 10:70 channel decompression with deskew capability
Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 11.9Gb/s (1.487Gbytes per second).
Suitable for 3DTV (FullHD @120Hz)
Two (2) instances can provide FullHD @240Hz.
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FPD IP
- LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
- LVDS/FPD Link IP, Silicon Proven in GF 28LPe
- FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- LVDS serdes 28:4 channel compression TX 20-170Mhz