V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined signals).
Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 11.9Gb/s (1.487Gbytes per second).
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
- +/-0.3 UI bus de-skew, relaxes timing constraint
- Input clock detector (self reset when missing clock)
- Spread-spectrum input clock support (can be used in SS systems)
- Core cell area : [contact us]
- Power consumption [contact us] @150Mhz
- Built-in power pads with ESD protection.
- Low leakage power-down mode <1uA.
- Design kit includes :
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- This interface is suitable for TCON chips inside Flat panel displays, as a FPD-Link receiver.