Fast Floating Point Option for the DesignWare ARC HS4x and HS4xD Processors
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Gen5 PCIe Transparent Switch
Mobiveil's PCI Transparent Switch is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.
GPEX-SWITCH is part of Mobiveil’s PCI-Express (GPEX) family of IP solutions which includes End Point (GPEX-EP), Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
GPEX-SWITCH leverages Mobiveil’s years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and interoperability.
GPEX-SWITCH is part of Mobiveil’s PCI-Express (GPEX) family of IP solutions which includes End Point (GPEX-EP), Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
GPEX-SWITCH leverages Mobiveil’s years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and interoperability.
特色
- Compliant to PCI Express base specification 5.0 (32 Gbps per lane) and backward compatible with PCI Express versions 4.0, 3.1, 2.0 and 1.1
- Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
- Architected for high link utilization and low latency
- Non-blocking architecture
- 32/ 64/ 128/ 256/ 512 bit Datapath
- Each port can support a unique feature set
- Completely handles PCI-Express ordering rules
- Implements flow control logic for both directions
- Optional AMBA Master and Slave Interface to the Application logic
- 8bit/ 16-bit/ 32-bit/ 64-bit Pipe interface for external ports on link side that supports PIPE5.0 compliant PHYs
- Support for link re-configuration, programmable link width on multi-lane ports
- Supports parallel address decoding at each ingress port
- Advanced Error reporting for all switch ports and embedded endpoints
- Full PCI-PM and ASPM Support for L0s, L1 and L1 PM Substates
- Configuration access to internal ports and type-1/ type-0 conversion for configuration transactions
- Unsupported request and unexpected completion handling for both upstream and downstream traffic
- Round Robin and Strict Priority arbitration with starvation detection options for Port Arbitration
优势
- Configurable Options
- Maximum Link Width (x1, x2, x4, x8, x16)
- Maximum TLP data payload size supported (128B to 4KB)
- Data Path Widths (32, 64, 128, 256 and 512 bit)
- 8-bit/ 16-bit/ 32-bit/ 64 bit PIPE interface
- Transmit Retry / Receive Buffer size
- Number of Virtual Channels
- Upstream port / downstream port
- Inclusion of specific sublayers etc
- ASPM L1/ Wake support, Auxiliary power support
- L1 PM Substate Support
- Hot plug support
- Design Attributes
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
- Multiple loop backs for debug
可交付内容
- Verilog RTL Code
- UVM based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation
- Design Guide
- Verification Guide
- Synthesis Guide
应用
- PC’s workstations and servers
- Storage
- Networking and communications
- Switches and routers
- General purpose system chip interconnect for any compute platform
Block Diagram of the Gen5 PCIe Transparent Switch
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PCI Express Switch IP
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
- PCIe 5.0 Controller
- Customizable Embedded Multi-port PCIe Switch
- Gen5 PCIe Root Complex Controller with SR-IOV and ARI Support
- Gen5 PCIe Endpoint Controller with SR-IOV and ARI Support