10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
控制器IP为PCIe 5.0, 4.0, 3.1/3.0支持根端口,端点,双模式配置,可选内置DMA和可配置AMBA AXI互连
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Block Diagram of the 控制器IP为PCIe 5.0, 4.0, 3.1/3.0支持根端口,端点,双模式配置,可选内置DMA和可配置AMBA AXI互连
DMA Engine IP
- Multi-Protocol Crypto Engine
- Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached
- Lancero Scatter-Gather DMA Engine for PCI Express
- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect