The SDDR Reference Regulator has been designed to provide 0.625-0.99V with a load current of up to 1mA, having a low area and high accuracy.
The SDDR Reference Regulator features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output while maintaining minimum ripple on supply lines in the presence of load current spikes inherent with switching loads, e.g. DDR memory.
The DDR Reference Regulator has been designed to allow lowdrop operation in a low area (the PMOS pass device has been scaled for a voltage drop of no less than 600mV). To achieve these goals, the S3REG115GF18 requires an external ceramic capacitor.
- 0.18um GF IC Process
- 1.5V Input Voltage
- 0.625V – 0.99V Output Voltage
- 1mA Load Current
- Very Compact Die Area: 0.041 mm2
- Leakage: 1uA
- Power Down Mode
- Power Good Detection
Block Diagram of the DDR Reference Regulator