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Bandgap Voltage / Current Reference TSMC
The agileBandGapGP consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of output bias currents can be specified up to a maximum of 16 configurable outputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable, leading to analog IP that is more verifiable, more robust and more reliable.
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Block Diagram of the Bandgap Voltage / Current Reference TSMC
LDO IP
- Low Dropout (LDO) Capless Regulator
- Voltage Regulator LDO, Adjustable 1.1V Output
- 40nm 1.8V Programmable 1.1V LDO Regulator with 50mA max. output
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
- Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply)
- Capless low input voltage LDO in GlobalFoundries 22FDX