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Lvds IP Listing

519 IP Cores (281 - 320)

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MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)

Egis Technology Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the rigorous demands of next-generation ...

281
Color Camera Sensor Bayer Decoder

Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern. Bayer filter in front of the sensor embeds color information into sensor's pixels and each ...

282
Camera Link Interface

The Camera Link® IP Core is a high-speed LVDS transmitter / receiver pair that conforms to the standard Camera Link protocol originally developed by National Semiconductor Corp®. The design ...

283
V-by-One Tx IP，在 SMIC 40LL 中经过硅验证

V-by-One HS技术是针对基于设备内部连接的视频信号的高速数据传输。V-by-One®HS标准定义了开发Rx和Tx标准。这个PHY IP支持4Gbps/通道的传输速率，并为Tx和Rx提供了8通道和16通道的...

284
V-by-One Rx IP，在 SMIC 40LL 中经过硅验证

V-by-One HS技术旨在通过内部设备连接以高数据速率传输视频信号。这个PHY IP支持4Gbps/通道的传输速率，并为Tx和Rx提供了8通道和16通道的多通道传输。

285
V-by-One Tx IP，硅在 40G 中得到验证

V-by-One HS技术旨在利用设备之间的内部连接以高数据速率传输视频信号。在Vby-One®HS标准中列出创建发射器和接收器的要求。这个设计具有8通道和16通道物理层（PHY）用于发送（Tx）...

286
V-by-One Rx IP, Silicon Proven in 40G

Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate. The V-by-One HS Standard outlines the requirements for producing a transmitter ...

287
1.25 Gbps SGMII SerDes

MXL-SRDS-SGMII is a Serial Gigabit Media Independent Interface SerDes implemented in digital CMOS technology. The SerDes IP offers data transfer rate of 1.25Gbps, for both upstream & downstream ...

288
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process

10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process

289
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process

The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process

290
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process

The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process

291
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process

The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process

292
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process

The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process

293
100MHz single-ended to differential clock buffer for UMC 40nm LP.

100MHz single-ended to differential clock buffer for UMC 40nm LP.

294
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

295
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process

1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process

296
MIPI D-PHY Transmitter 2.5Gbps 4-Lane

The CL12631I4T1AS1BIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12631I4T1AS1BIP2500 converts the input parallel data to the serial data ...

297
MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane

The CL12661K4T1AM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12661K4T1AM2JIP is designed to support data rate in excess of maximum 1.5Gbps ...

298
Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane

Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12832M8R2JM3KIP2400 is designed to support data rate in excess of maximum 2.4Gbps utilizing SLVS-EC / sub-LVDS / CMOS 1.8V interface ...

299
MIPI D-PHY TX/CSI2 Link Controller

CD12631S4TIP is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting input data ...

300
Multi-PHY Receiver Link Controller

CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting ...

301
3.125 Gbps DDR 1-channel CML transmitter

065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter state and control pin EN_PR to toggle pre-emphasis ...

302
Programmable Special IO in SMIC0.13um

AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extremely suitable for FPGA/MPGA design where special ...

303
Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)

Now available up to 170 Mhz per channel ! This FPD Link Transmitter Macro is based on National emiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital ...

304
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

305
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

306
显示接口复用器

便携式计算机电源管理的最新趋势是可切换图形。这项技术可以使一块独立显卡在直流电源（插到电源插座）供电的情况下用于图形密集型应用，同时也能使Intel集成显卡工作于电池模式时...

307
Mini-LVDS TX and RX PHY

The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process. It is suitable for the interface between the timing controller and column drivers.

308
Sub-LVDS receiver followed by 1:4 de-serializer

The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word. The receiver defined in this IP is only required to interface with the image ...

309
32:1 serializer followed by sub-LVDS drivers

The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in subLVDS mode only, which is defined in the ...

310
Display Controller - LCD / OLED Panels (AHB Bus)

The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an ASSP, ASIC, or FPGA, typically, ...

311
Compact Multilayer Video Controller

The logiCVC-ML IP core is an advanced display graphics controller that enables an easy video and graphics integration into embedded systems with the Xilinx FPGAs and Zynq-7000 AP SoC. It can ...

312
SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY

Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process Fully in compliance with ANSI, Bellcore and ITU jitter Specifications Proven in ...

313
Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain

PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32. The serializer (except 32 bit outputs) is implemented based on differential CML logic for robust ...

314
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain

PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU, loop-backs, LOL, LOS, Equalizer, LA, line rate output driver. ...

315
Physical Layer Interface Core

Fully Compliant with Rapid Interconnect Specification Rev 1.1, 3/2001 prescribed by Rapid Trade Association. ; 32-bit standard Host/Link Interface. ; Full Duplex Independent Transmit and Receive ...

316
POS-PHY Level 4

The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet ...

317
Serial GMII 1.25 Gbps Phy

SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interface to MAC layer and consists of Physical Convergent Sublayer ...

318
10/100/1000 Ethernet (Triple Speed)

As the leading provider of 1 Gbps Ethernet (GbE) for FPGA and HardCopy® ASIC devices, Altera offers the Triple-Speed Ethernet MegaCore® function, allowing you to easily build systems with ...

319
10Base-T Interface - requires no PHY

Full support for 10Base-T, full- or half-duplex

320

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