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If digitizer IP Listing

438 IP Cores (241 - 280)

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400G OTN 转发器（附有AES功能）

Callite-C4提供了一个动态可重新配置的400GE或4x100GE至4xOTUC4，2xOTUC2或1xOTUC4 转发器/多路复用转发器的解决方案。它是一个单一的基于 ASIC/FPGA的SOC解决方案。所有SOC解决...

241
OTU0/ODU0数据封装器

OTU0/ODU0数据封装器IP依据ITU-T G.709规定，通过光纤传输网络（OTN）提供1.25 G/s客户端传输速率。简介在源接入方向上（source direction），数据通过异步fifo从客户时钟...

242
OTU1 (2.5G/s)数据封装器

OTU1数据封装器IP依据ITU-T G.709规定，通过光纤传输网络（OTN）提供2.5G/s客户端传输速率。简介在源接入方向上（source direction），数据通过异步fifo从客户时钟传输到...

243
OTU2 / 2e (10G/s) 数据封装器

OTU2/2e数据封装器IP依据ITU-T G.709规定，通过光纤传输网络（OTN）提供10G/s客户端传输速率。简介在源接入方向上（source direction），数据通过异步fifo从客户时钟传输到...

244
40G OTN Digital Wrapper

OTU3数据封装器IP依据ITU-T G.709规定，通过光纤传输网络（OTN）提供40G/s客户端传输速率。简介在源接入方向上，数据通过异步fifo从客户时钟传输到线路时钟生成ODU / OTU帧...

245
OTU4 (100G/s) 数据封装器

OTU4数据封装器IP依据ITU-T G.709规定，通过光纤传输网络（OTN）提供100G/s客户端传输速率。在源接入方向上（source direction），数据通过异步fifo从客户时钟传输到线路时钟...

246
24 Ghz / 77 Ghz Automotive Radar Transceivers IP

Driver assistance systems use radar sensors in various counts and configurations. The data provided by the radar sensors is used in applications such as blind-spot detection, autonomous emergency ...

247
AM / FM Tuners IP

Powerful and cost-efficient scalable platform from low to (very) high end • True SDR Processor • World-Wide Receiver • Upgradable • Prepared for the challenges of the future radio ...

248
GNSS超低功耗（GPS，Galileo，GLONASS，Beidou3，QZSS，IRNSS，SBAS）数字IP

超低功率GNSS 多星座数字IP从包含GPS, GALILEO, GLONASS, Beidou3, QZSS, IRNSS / NAVIC等所有主要星座的芯片组合中提取出来。在链接到适用的RF接收器时，该数字IP支持同时接收多...

249
MIPI CSI-2 Receiver v2.0 控制器IP，兼容MIPI C-PHY & D-PHY

MIPI CSI-2是一个在相机和主机处理器基带应用引擎之间的接口，由MIPI联盟定义。这个接口定义了一系列模块，用于在符合MIPI规范的产品中使用。MIPI CSI-2接收器用于移动和高速串行...

250
Linear Regulator, Low quiescent current

The qLR-Aubrey-ref-[1.62-3.63]-[1.2-3.3]-I0.3-Iq200.01 is an ultra-low-quiescent-current regulator used to generate SoC internal supply for retention logic islets. qLR-Aubrey-ref-[1.62-3.63]-[1.2-3.3]-I0.3- ...

251
9 track Near Threshold Voltage standard cell library at TSMC 55 nm

TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the supply voltage for always-on logic and retention ...

252
32-bit, 33 MHz PCI Target Interface Core

The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. ...

253
100G UDP/IP硬件协议栈

实现了UDP / IP硬件协议栈，该协议栈支持通过LAN或点对点连接进行高速通信。该内核专为独立运行而设计，非常适合将主机处理器从繁重的UDP / IP封装工作中解脱出来，即使在无处理器...

254
Secure AHB Performance Subsystem - ARM M3

The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It integrates a security conscious processor, ...

255
Dolphin I3C Controller & PHY

DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C bus. The IP facilitates software controllable ...

256
Dolphin Watchdog Timer (WDT)

Dolphin Technology provides Watchdog Timer (WDT) IP which is used to prevent system lockup if software becomes trapped in a deadlock by generating a system reset, an interrupt, or an external ...

257
Power Management Unit

PMU is designed to supply integrated circuits with stable and precise voltage. 055UMC_PMU_01 is a library including RS block and 4 LDOs: LDO1 to supply digital circuits; LDO2 and LDO3 to supply ...

258
Power Management Unit

PMU IP includes following components: Bandgap reference voltage source and reference current sources. Bandgap source forms temperature, power supply and process variations independent voltage. ...

259
Ethernet Switch / Router IP Core - Efficient and Massively Customizable

Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide an optimized custom IP core within days ...

260
32-512 Point Streaming FFT

The FFT1-32-512/4 core implements 32, 64, 128, 256, and 512 point FFT and IFFT in hardware that runs at the clock frequency four times higher than the input sampling frequency.

261
IEEE 802.11ax MAC/PHY for STA

IEEE 802.11ax is a Wireless Local Area Network standard in the IEEE 802.11 set of specifications. It is also labelled as Wi-Fi 6 by Wi-Fi Alliance. IEEE 802.11ax is designed to operate in the ...

262
ITS-G5/802.11p PHY/MAC

IEEE 802.11p is an approved amendment to the IEEE 802.11 standard to add wireless access in vehicular environments (WAVE), a vehicular communication system. It defines enhancements to 802.11 ...

263
IEEE 1588 IP

IEEE 1588 core is compliant with IEEE Standard 1588-2019 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. IEEE 1588 IIP is proven ...

264
ECC with BCH Algorithm

The IntelliProp IPC-BL119A-ZM is a highly configurable IP core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across ...

265
SATA Port Multiplier with Sandbox

The IntelliProp IPP-SA128A-PM (SATA Port Multiplier with Sandbox) device is an IP core that provides SATA Port Multiplier functionality with support for up to 15 SATA storage devices. The IP ...

266
Low Voltage, Low Power Fractional-N PLLs

Perceptia’s DeepSub™ pPLL05 is a family of low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and embedded clocking applications in systems ...

267
Low Voltage, Low Power Fractional-N PLL

Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and embedded clocking applications in systems running ...

268
Phase Locked Loop (PLL) Macro

The PLL consist of the PLL loop, lock detect circuit and 9 output counters. The delta sigma modulator & spread-spectrum clock generation logic is placed in the core (PLL wrapper) and can be ...

269
PCIe Multifunction IP Core for Xilinx 7 FPGAs

The PCI Express Specification allows Endpoints that incorporate more than one physical PCIe-Function. Such Endpoints are called Multi-Function Devices. The big advantage of a Multi-Function ...

270
Partial Reconfiguration Bitstream Monitor IP

The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design. This information can be used for debugging or to help manage system ...

271
High Throughput and Low Latency Data Compression Engine

This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very high compression ratio. This IP can be used stand alone in data ...

272
Low Latency Interconnect for AI/ML (GreenIPCore Shared Multi Memory Integration Controller (SMMIC))

Low Latency Interconnect for AI/ML developed with Advanced Low Power methods and Design Architecture solves Routing Congestion, Delay in Command priority and latency issues. Low Power Edge AI/ML ...

273
Video Tracking FPGA IP core for Xilinx and Altera

The FPGA IP core T-COR-32 implements the algorithm of automatic tracking of objects in video and calculation of their motion parameters. The core ensures a stable tracking of small-sized and ...

FPGA IP CORE VIDEO TRACKING (T-COR-32)

274
Fault Resistant Clock and Reset Monitor

This is a Clock and reset monitor block. It monitors clock and reset signals and report if there are changes in clock beyond a certain range of frequencies and glitches on reset signals.

275
32bit 33/66MHz PCI Core w/Cardbus support

The Inventra™ MPCI32 PCI Peripheral Soft Core implements the PCI Master/Target function for 32bit peripherals connecting to a 32bit PCI Bus. The core is factory-configurable for up to ...

276
DO-254 ARINC-429 Receiver

The ARINC 429 Rx IP Core implements a receiver as specified in the ARINC Specification 429 Part 1-17. This “Mark 33 Digital Information Transfer System (DITS)” specification defines how ...

277
DO-254 ARINC-429 Transmitter

The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17. This “Mark 33 Digital Information Transfer System (DITS)” specification defines ...

278
DO-254 I2C Master

The I2C Master IP Core implements an I2C Master fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+). ...

279
DO-254 I2C Slave

The I2C Slave IP Core implements an I2C Slave fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+). ...

280

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