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DO-254 I2C Slave
The I2C Slave IP Core implements an I2C Slave fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+).
The Inter-Integrated Circuit (I2C) is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). The I2C bus is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers.
The I2C Master IP Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Safe Core Devices provides two separate IP Cores, one for the I2C Slave IP Core and one for the I2C Master IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
The Inter-Integrated Circuit (I2C) is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). The I2C bus is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers.
The I2C Master IP Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Safe Core Devices provides two separate IP Cores, one for the I2C Slave IP Core and one for the I2C Master IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
查看 DO-254 I2C Slave 详细介绍：
- 查看 DO-254 I2C Slave 完整数据手册
- 联系 DO-254 I2C Slave 供应商
Block Diagram of the DO-254 I2C Slave
I2C IP
- TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell