The PLL consist of the PLL loop, lock detect circuit and 9 output counters. The delta sigma modulator
& spread-spectrum clock generation logic is placed in the core (PLL wrapper) and can be removed if
fractional division is not needed.
- Support programmable bandwidth
- Support spread-spectrum reference clock tracking
- Triangular Modulation frequency: less than 75KHz
- Down spread or center spread : less than 2.5% (p-p)
- Support internal feedback (internal compensation) and external feedback (external compensation).
- Programmable reference clock divider, feedback clock divider, output clock divider (up to 512 division).
- Output counter
- No. of output counter: 9
- Support output counter cascading.
- Support programmable duty cycle output counter.
- Support 1/8 VCO clock period phase shift.
- Support output inversion
- All output counters are synchronized on startup
- Support PLL cascading
- 2 instances of PLL can be cascaded. eg. output of PLL #1 is used as input reference clock for PLL #2.
- Proper startup sequence is required, eg. enable PLL #2 after PLL #1 is locked.
- Support fractional division and SSC generation (digital logic is implemented outside the macro, in PLL wrapper RTL)
- Hard-IP - physical layout (GDSII) for GlobalFoundries 40nm LP process
- LVS/CDL netlists
- Verilog simulation models (Tetramax and ATPG compatible)
- Synopsys Liberty files
- Physical LEF (Cadence)
- Specification, integration, and usage documentation