The 14-Bit Dual Pipeline ADC is operating up to 19.2MS/s and dissipating 71.5mW at 19.2MS/s, including auxiliary circuits.
The 14-Bit Dual Pipeline ADC employs a high-performance front-end input sample-and-hold circuit together with a differential pipeline architecture and digital error correction. This ADC IP features an excellent static performance that includes ±0.8LSB DNL and ±4.0LSB INL at 14-bit resolution.
Dynamic performance highlights considering an input signal with 0.8MHz frequency and 19.2MS/s sampling rate include an SNR of 65.5dB, SFDR of 73dB and 10.3-bit ENOB measured over Nyquist.
Auxiliary circuits comprising a bandgap circuit, operating mode controls and voltage reference buffers with external decoupling are also included to provide a complete ADC solution.
The 14-Bit Dual Pipeline ADC can be cost-effectively ported across foundries and process nodes upon request.
- TSMC 0.18um Mixed-Signal RF
- Dual 1.8V and 3.3V Power Supplies
- 19.2MS/s Maximum Sampling Rate
- 2.0Vpp Differential Input Range
- DNL= ±0.8LSB Typ.; INL= ±4.0LSB Typ.
- SNR= 65.5dB at fin= 0.8MHz and 19.2MS/s
- SFDR= 73dB at fin= 0.8MHz and 19.2MS/s
- 10.3-bit ENOB at fin= 0.8MHz and 19.2MS/s
- Stand-By and Power-Down Modes
Block Diagram of the 14-Bit 19MS/s Dual Pipeline ADC