Ridgetop’s silicon-proven ADC is optimized for high performance imaging applications and other high data rate, high SNR applications. This ADC is designed for the TSMC 180 nm mixed-mode process using MIM capacitors. The ADC has fully differential variable gain input, and has pipeline architecture with 1.5 bits-per-stage resolution, with digital error correction. Each stage makes two conversions per clock cycle, resulting in a 2-bit output. The architecture allows individual ADC stages to be scaled and optimized for both noise and power. Figure 1 shows GDSII layout, Figure 2 illustrates the ADC pipeline architecture, and Table 1 outlines the ADC specifications.