You are here:
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Control is managed by Descriptors initialed by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
Control is managed by Descriptors initialed by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
查看 DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List 详细介绍：
- 查看 DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List 完整数据手册
- 联系 DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List 供应商
Block Diagram of the DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
AXI4-Stream Interface IP
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
- CCIX 1.1 Controller with AMBA AXI interface