The Rianta Solutions RS1011 10GBASE-W/R/X/T PCS block is fully verified IP suitable for integration into FPGA or ASIC solutions for multiple packet applications. Implemented in Verilog with comprehensive testbench support, the RS1011 includes a configurable PCS supporting all 10GBASE types. In addition, the RS1011 supports both direct and remote connection to a Reconciliation Sublayer (RS) via XGMII or XAUI.
特色
- Optional XGXS
- XAUI Interface to remote RS
- 8B/10B encoding/decoding of XGMII lanes
- interframe insertion/deletion for clock compensation
- XGMII interface to local RS
- 32-bit Data
- 4-bit Control
- 10GBASE-W/R
- 64B/66B encoding/decoding (10GBASE-W/R)
- Scrambling/descrambling (10GBASE-R)
- WIS encapsulation (10GBASE-W)
- 10GBASE-X
- 10GBASE-T
- LDPC encoding/decoding
- Scrambling/descrambling
- Auto-negotiation
- Detection and generation of fault and control codes
- Full duplex
- Loopback and test pattern support
应用
- Packet Processing
- Packet Transport
- Packet Optical Transport Systems (POTS)