The ADC is a high speed pipelined analog-to-digital converter specified to operate from a nominal 1.8V analog supply and 1.8V digital supply with tolerances of up to 10%. By implementing an 8-stage pipelined architecture with alignment and output error correction logic, the ADC offers accurate performance and guarantees no missing codes over the full operating temperature range. This complete converter includes as well as biasing block, a clock generator and an output buffer.
The ADC employs digital correction techniques to provide good differential linearity for communication applications.
The ADC can be placed into a power down standby mode of operation reducing power to below 1 mW. The format of the output is unsigned binary coding.
The ADC is compact and occupies 1.4mm x 2.2mm of die area in mixed signal MIM 0.18um CMOS process. The fully differential architecture makes it insensitive to substrate noise coupling. Thus it is ideal as a mixed signal ASIC macro cell.
All interface signals are 1.8V based, providing customers flexibility to directly integrate into design core.
- 1) High speed pipeline architecture
- 2) 1.8V analog supply and 1.8V digital supply operation
- 3) Differential input range: -0.5V to +0.5V
- 4) 0.18 um mixed signal technology
- 5) Utilizes CMOS process (MIM and HR poly)
- 6) Core size: 1.4 mm x 2.2 mm
- 7) Sampling rates up to 80 Msps
- 8) Low power supply current: 49 mA
- 9) Power down mode
- 10) Integral Nonlinearity: -/+1LSB
- 11) Differential Nonlinearity: -/+0.5LSB
- 12) SNDR: 56dB
- 13) Guaranteed no missing codes
- 14) Resolution: 10 Bit
- 15) Low input capacitance
- 1. Internal reference
- 2. Compact Die Area
- 2.Flat Netlist (cdl)
- 3.Layout View (gds2)
- 4.Abstract View (lef)
- 5.Timing View (lib)
- 6.Behavioral Model (Verilog)