This Analog -to-Digital converter IP has a monolithic differential pipelined architecture with output error correction logic providing 10 bits conversion accuracy from 10 up to 110 Mhz sampling frequency.
It is designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V.
This ADC can interface with both 1.8V or 3.3V core logic, by connecting dvdd to 1.8 or 3.3V power line, giving more flexibility for design reuse.
- 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
- single power supply: 3.3V
- Resolution: 10bit
- Clock Frequency: 110 MHz
- 9 stages of 1.5b pipeline architecture with digital correction
- Power consumption: (contact us)
- Layout Area (contact us)
- This ADC is suitable for :
- High Definition video sampling,
- standard video sampling,
- high speed analog front-end for digital core,
- triple video ADC capture
- communication AFE
- LVS netlist
- LIB timing
- LEF abstract
- Verilog/VHDL model
- Application Notes