The present IP is a VCC Detector (VDT) circuit. It detects the core supply and gives a control signal to level shift. It detects the voltage level of input voltage VDD18, of which the normal operation voltage range is 1.62V~1.98V. when the detected supply voltage (VDD18) increases above the detection level (VR18), the corresponding output V18_RY is generated as a high level logic(V33) whereas V18_RYN as a low level logic; when the detected voltage(VDD18) decreases below the detection level(VF18), the corresponding output V18_RY is generated as a low level logic whereas V18_RYN is generated as a high level logic. This IP supports 90% direct shrink.