The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution.
The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video.
The H264-D-BP is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder’s memory interface—used to store reconstructed video data—is extremely flexible: it operates on a separate clock domain, is independent from the external memory type and memory controller, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.
- Constrained Baseline Profile AVC/H.264 decoder
- Ultra-Low-Latency: less than one msec latency for most widely used formats
- High performance: 2.5 cycles per pixel; Full-HD capable
- ISO/IEC 14496-10/ITU-T H.264, Constraint Baseline Profile specification
- I and P slices
- Multiple slices per frame
- Multiple reference frames
- Multiple sequence parameter sets (SPS)
- Multiple picture parameter sets (PPS)
- In-loop deblocking filter
- CAVLC entropy decoding
- Real time performance up to level 4.1
- Video Formats
- Progressive, 4:2:0 YCbCr with 8 bits per color sample
- From QCIF (176x144), to 2048x2048 resolutions
- Low Latency
- No decoded frame buffering
- Decoded pixels are streamed-out output with less than one macro-block lines of latency
- Less than 1 msec for almost all widely used video formats
- Ease of Integration
- Zero CPU overhead, stand-alone operation
- AMBA® AXI external memory interface: uses separate clock, is independent of memory type and tolerant to latencies
- Streaming interfaces for bit-stream and pixel data, with flow control; easily bridged to AMBA® AXI Streaming
- Error catching and reporting capability
- Reports video format and enables cropping
- Optional Block to Raster
- Silicon proven
- Verified with Fraunhofer H.264 Compliance Test Streams suite
- Source-code VHDL (ASICs) or as a targeted netlist (FPGAs)
- Sophisticated self-checking Testbench
- Synthesis scripts.
- Simulation script, vectors and expected results.
- Software Bit-Accurate Model
- Comprehensive user documentation
- The H264-D-BP is suitable for broadcasting, surveillance, industrial, defense, and medical live-streaming applications with low-latency requirements and resolutions up to Full-HD.
Block Diagram of the Low-Latency AVC/H.264 Baseline Profile Decoder Core