USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
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USB 3.2 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.2 OTG controller are designed for compliance with USB 2.0 specification Revision 2 0 and all associated ECN’s and USB OTG EH 2 Revision 1.1a and all associated ECN’s While operating in Host mode, based on configuration selected, it is compliant with xHCI enabling standard Windows, Linux, Android drivers to be reused minimizing software development overheads and associated risks involved with custom bare metal driver solutions Its Physical interface is compliant with USB Pipe Specification v 4 3 (for SS/SSP lane rates) and ULPI+ or 8 16 bits UTMI PLUS Level 3 specification (for HS/FS/LS mode) The system interface is compliant with either AHB and/or AXI interface allowing easy integration Optional custom bridges can be bundled as a service offering.
USB 3.2 OTG controller, while operating in device mode, can optionally include a proprietary high performance DMA engine for moving USB payloads The register interface of the DMA Engine is very simple allowing device side class specific function drivers to be implemented easily Reference mass storage class device side function drivers are made available to all licensees All buffering associated with the DMA Engine are configurable based on latency and performance requirements.
USB 3.2 OTG controller, while operating in device mode, can optionally include a proprietary high performance DMA engine for moving USB payloads The register interface of the DMA Engine is very simple allowing device side class specific function drivers to be implemented easily Reference mass storage class device side function drivers are made available to all licensees All buffering associated with the DMA Engine are configurable based on latency and performance requirements.
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Block Diagram of the USB 3.2 OTG High / Full / Low- Speed Dual Role IP Core
USB IP IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software