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Ultra-Low Jitter Fractional-N PLL
This ultra low jitter PLL (<1.2ps-rms LT jitter) has been implemented for use with S3's high-resolution, high-performance A/D converters, where low jitter clock generation is critical to the success in high speed, high resolution applications, such as Cable Modem, LTE and communications infrastructure systems.
特色
- TSMC 180nm CMOS Process
- Junction Temperature Range -40ºC to +125ºC
- 24-bit Frequency Resolution (typ. 1Hz)
- Frequency-Hop Sensitive Lock Detect
- Integrated VCO Calibration
- VCO Phase Noise -127 dBc/Hz at 1MHz Offset
- PLL Phase Noise Floor -217dBc/Hz
- Reference Clock Frequency: 1MHz to 50MHz
- VCO Frequency 1.65GHz to 1.85GHz
- Output Frequency 5MHz to 300MHz
- Ultra-Low Spurious: < -68dBc
- Long-Term Jitter < 1.2ps-rms Typ.
- Fast Lock Time < 11us
- Power-Down and Reset Modes
- Integrated Inductors
- Low Power Consumption
- Small Die Area
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