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Display Stream Compression (DSC 1.2) Decoder
The Display Stream Compression (DSC) standard from the Video Electronics Standards Association (VESA) offers visually lossless compression for high definition (HD) video in broadcast, automotive, medical and consumer electronics applications. The Trilinear Technologies M25 DSC 1.2 Decoder offers real time decompression of HD streams with resolutions from 480p up to 8K. The decoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC platforms.
The M25 core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and decoder control. The encoded input interface is AXI4-Stream Protocol compliant and the output interface uses a streaming data structure with associated line and frame formatting signals. The DSC 1.2 Decoder core supports 8, 10, 12, 14 or 16 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.
The M25 DSC 1.2 Decoder core ships with a complete ‘C’ reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Cobra Development platform based on the Xilinx Kintex-7 FPGA family. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
The M25 core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and decoder control. The encoded input interface is AXI4-Stream Protocol compliant and the output interface uses a streaming data structure with associated line and frame formatting signals. The DSC 1.2 Decoder core supports 8, 10, 12, 14 or 16 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.
The M25 DSC 1.2 Decoder core ships with a complete ‘C’ reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Cobra Development platform based on the Xilinx Kintex-7 FPGA family. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
特色
- Overview
- VESA DSC 1.2 Compliant
- Capable of decoding 4K video at 30fps in FPGA and ASIC
- Decode 8K video at 30fps in ASIC applications
- Low gate count implementation
- Low latency implementation
- Decoder Details
- RGB or YCbCr encoded input
- 8, 10 or 12 bits per color
- 4:2:0 and 4:2:2 support
- AXI 4 Stream Input Interface
- AMBA 3.0 APB Host Interface
- Reference Software
- Complete reference driver
- Stream decoder sample application
- C source code provided
- FPGA Development Platform
- 32-bit MIPS CPU based system
- HDMI Video Output
- Optional DisplayPort 1.3 output
- SD Card Stream Storage
- Hardware Driver and Reference Encoder Included
Block Diagram of the Display Stream Compression (DSC 1.2) Decoder
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VESA DSC IP
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- VESA DSC (Display Stream Compression) 1.1 Video Encoder
- VESA DSC (Display Stream Compression) 1.1 Video Decoder
- VESA DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs