You are here:
Display Stream Compression (DSC 1.2) Decoder
The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel using either RGB or YCbCr in 4:4:4 or 4:2:2 format. The DSC Decoder core integrates industry standard interfaces for host configuration and control, data input, and video output.
查看 Display Stream Compression (DSC 1.2) Decoder 详细介绍：
- 查看 Display Stream Compression (DSC 1.2) Decoder 完整数据手册
- 联系 Display Stream Compression (DSC 1.2) Decoder 供应商
Block Diagram of the Display Stream Compression (DSC 1.2) Decoder
VESA DSC IP
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder