Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz

A programmable fully digital PLL designed to lock to an incoming clock source and produce an output clock. It is ideal as a clock generator for digital designs, but not intended for analog blocks like ADC/DAC or SERDES clocking. This digital PLL has ultra-low area and low implementation charges due to predictable digital design.

• 查看 Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz 完整数据手册
• 联系 Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz 供应商