subLVDS IO Pad Set
Using this SubLVDS Pad Set, the system can achieve very high data rates per pin with simple termination requirements and low EMI. The driver has been optimized for speed/power and can be ported to various pure digital CMOS processes from 0.18μm down to 28nm technologies. The LDP_OU_450_18V_T has been optimized for 1400MBit/s operations. The receiver has been designed with no hysteresis in order to optimize sensitivity and skew.
The driver design has all the necessary components for transmit of SubLVDS data and a temperature stable internal reference for setting of the SubLVDS signaling voltage and common mode level. This provides user flexibility in deploying multiple SubLVDS transmitters. The reference block is required for the SubLVDS drivers to provide a stable common mode voltage as well as an accurate current reference for the driver source / sink current. Maximum operating frequency is 700 MHz.
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