Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
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Single Precision Floating Point Multiplier
Single precision (32bits) IEEE 754- 2008 standard Floating Point pipeline Multiplier IP core achieve the high throughput in the FPGA/ASIC platforms. In Arria10 FPGA Device it can achieve maximum operating clock frequency of 173MHz and throughput of 173MSPS with 3 clock cycle initial latency.
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Floating Point Multiplier IP
- Floating point multiplier
- Single precision, IEEE 754, floating point multiplier
- Single Precision Floating Point Complex Multiplier
- Single Precision Floating Point Complex Matrix Multiplier [NXN]
- Half precision, IEEE 754, floating point fused multiply add
- Low power 32-bit processor supporting single precision floating point in hardware