The S3PORTC90FS is a low-power reset circuit that provides the following feature:
Power-On Reset (POR) signal that monitors the absolute value of two supplies. The logic level of this reset signal is set by the level of the power supplies and can be delayed by an internal RC oscillator and counter.
The internal RC oscillator can also be used to drive other circuitry if required
During sleep mode which requires low power RC oscillator generates a very low clock frequency
The S3PORTC90FS uses a threshold detect circuit to establish the point when it is safe for circuitry to begin functioning. This detection circuit guarantees that the supply is at a sufficient level for the circuitry to operate correctly.
The POR output signal can be delayed by varying amounts, should it be required by changing the counter division.
- 90nm TSMC LP Flash Process, 4 Metals Used
- (No Analog Options)
- Power-On Reset output
- RC-Oscillator output >12MHz or >23KHz
- No External Components
- Power-Down and Test Modes
- Compact Die Area: 0.046mm2
- Analog Test Input Signal Port
- Sleep mode
- The S3PORTC90FS circuit is implemented in the TSMC 90nm low power process. It is readily portable across all foundries and process nodes upon request.
- Operating from a single supply the S3PORTC90FS has a small die area of only 0.046mm2, and be used with S3 Bandgap circuits.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- Reset generation and supply monitoring for any digital or analog circuitry
Block Diagram of the 来自于S3 Group应用于模拟/数字电路供电重置和监控的的POR。