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Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises of existing VLSI PLus IP cores, optimized for CSI2 multiplexing, and glue logic
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Block Diagram of the Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
MIPI CSI2 Multiplexer IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
- MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm